Intel MMX Technology

Abstract

The Intel MMX™ technology comprises a set of instructions to the Intel architecture (IA) that are designed to greatly enhance the performance of advanced media and communications applications.

These extensions (which include new registers, data types and instructions) are combined with the Single Instruction, Multiple Data (SIMD) Execution model to accelerate the performance of applications such as motion video, combined graphics with video, image processing, audio synthesis, speech synthesis and compression, 2D and 3D graphics, which typically use compute-intensive algorithms to accomplish the purpose.
All existing soft wares that don't make use of this technology will also run on the processor without modification. Presented below is an elementary treatise on this technology in a programmer's point of view.
MMX™ technology provides the following new extensions to the Intel Architecture (IA) programming environment.
1.Eight MMX™ registers (MM0 to MM7).
2.Four MMX™ data types
3.The MMX ™ instruction set
The MMX™ register set consists of eight 64-bit registers . The MMX™ instructions access the MMX™ registers directly using the register names MM0 through MM7. These registers can only be used to perform calculations on the MMX™ data types; they can never be used to address memory. Addressing of MMX™ instruction operands in memory are handled by using the standard IA addressing modes (immediate, register mode etc.) and the general purpose registers.
The MMX™ technology defines the following new 64-bit data types
1. Packed Bytes Eight bytes packed into one 64-bit quantity
2. Packed Words Four 16-bit words packed into a 64-bit quantity
3. Packed Double Words Two double words packed into a 64-bit quantity
4. Quad Word One 64-bit quantity

The bytes in the Packed Bytes data type are numbered from 0 to 7 and the lower order bits of a 64-bit data are placed in the byte 0 whereas the higher order bits in the byte 7. Similarly Packed Word data type contains 4 words numbered from 0 to 4 and the lower order 16 bits are placed in the 0th word. Similar is the case with the other two data types.
The MMX™ instructions move the packed data types (packed bytes, packed words or packed double words) and the quad word data types to and from the memory or from the IA general purpose registers in 64-bit blocks. However when performing arithmetic or logical operations on the packed data types, The MMX™ instructions operate in parallel on the individual bytes, as described by the Single Instruction Multiple Data Execution model.

The Single Instruction Multiple Data (SIMD)

The SIMD instruction model can access up to 8 bytes at a time for arithmetic or logical operations using a single instruction at a time. Thus theSIMD Technique speeds up the software performance by allowing the same operation to be carried out on multiple data items in parallel. The MMX™ technology supports parallel operations on byte, word, and double word data elements when stored in MMX™ registers.